1. Field of the Invention
The present invention relates to a supply voltage generating circuit and a semiconductor memory device using the same. More particularly, the present invention relates to a power supply generating circuit which produces a supply voltage according to the period of a given clock signal, as well as to a semiconductor memory device having such a supply voltage generating circuit.
2. Description of the Related Art
The switching speed of digital devices largely depends on their load capacitance, which includes input capacitance of connected components and stray capacitance between circuit wires, and wires and ground. A digital device has to charge or discharge such load capacitance through its own output resistance, so that the voltage at a receiving end will rise above or fall below a predetermined threshold level. This charging or discharging action results in a certain amount of delay time, which is actually determined by the time constant of each particular circuit, i.e., the product of circuit resistance and load capacitance.
It is known that both resistive and capacitive components of such a digital circuit are almost constant, regardless of supply voltages applied. This implies that the load capacitance would charge up to, or discharge down to a certain voltage level (or threshold) in a shorter time if the source voltage was higher. That is, a higher supply voltage is required for higher switching operations. Stated in reverse, the devices can operate with a lower supply voltage when they are not required to operate so fast, and this fact suggests the possibility of dynamic power saving. Since a digital circuit consumes electric power in proportion to its supply voltage, the power consumption can be reduced by lowering the supply voltage when the clock signal is slow.
In an attempt to implement the above concept, researchers have proposed several methods to control supply voltages in connection with the clock signal frequency. Conventional methods use a threshold voltage of digital circuitry as the voltage step size for varying a supply voltage level.
Also, there has been a trend toward digital circuits that operate at a lower voltage. Devices operating at less than three volts, for example, are commonly used today. For those low-voltage devices, however, the use of such threshold voltages as 0.6 to 0.7V is not appropriate since it is too coarse to tune the supply voltage at a required resolution.
In view of the foregoing, it is an object of the present invention to provide a supply voltage generating circuit which can fine-tune its output voltages according to the frequency of a given clock signal.
Further, it is another object to provide a semiconductor memory device having such a supply voltage generating circuit.
To accomplish the first object, according to the present invention, there is provided a supply voltage generating circuit which comprises the following elements: a reference voltage generator which produces a plurality of reference voltages; a period measurement unit which measures the period of a given clock signal; a selector which selects one of the produced reference voltages according to the measured clock period; and a supply voltage generator which produces a supply voltage corresponding to the selected reference voltage.
To accomplish the second object, according to the present invention, there is provided a semiconductor memory device which comprises the following elements: a memory unit with an input/output interface which stores given data; a reference voltage generator which produces a plurality of reference voltages; a period measurement unit which measures the period of a given clock signal; a selector which selects one of the produced reference voltages according to the measured clock period; a supply voltage generator which produces a supply voltage corresponding to the selected reference voltage for use in the memory unit; and a voltage regulator which provides the input/output interface of the memory unit with a constant supply voltage that does not vary with the period of the clock signal.